A New Approach to Pipeline FFT Processor - Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International

A new VLSI architecture for realtime pipeline FFT processor is proposed. A hardware oriented radix-2’ algorithm is derived by integrating a twiddle factor decomposition technique in the divide and conquer approach. R a d i ~ 2 ~ algorithm has the same multiplicative complexity as radix-4 algorithm, but retains the butterfly structure of radix-2 algorithm. The single-path delay-feedback architecture is used to exploit the spatial regularity in signal flow graph of the algorithm. For length-N DFT computation, the hardware requirement of the proposed architecture is minimal on both dominant components: log, N 1 complex multipliers and N 1 complex data memory. The validity and efficiency of the architecture have been verified by simulation in hardware description language VHDL.